Open Silicon Conformance Matrix

The official RISC-V architecture tests, run against 11 open-source cores and compared with the Sail reference model. One agent runs each core; a different agent re-checks every failure before anything is reported.

Cores: 11
Tests passed: 1,596 of 1,649 run
No new deviation: 9 cores

Cores:
4 no deviation found
5 known upstream issues only
2 with new deviations (going to the maintainer first)

Not an official certification. Harness failures are problems in our test setup, not in the core, and the rate leaves them out. New deviations are counted, not described, until the maintainer has the report.

Results by core

How to read this

None: No failure traced to the core in the tests that ran.
Known upstream: The failures trace to behaviour the maintainers already know about: fixed, reported, discussed or documented upstream (linked), or tests on known issues.
N new: Confirmed and not known upstream. Shown as a count only until the maintainer has the report.
Spec deviations: Root causes, as checked by the second agent, not failing tests.
Rate*: Passed ÷ (passed + failed − harness failures). The bar runs from 0 to 100%.
Other failures: Harness: our test setup. Unresolved: differs from Sail, cause not yet pinned down.

11 cores, sorted by name
Core	ISA tested	Rate*	Pass	Fail	Spec deviations	Other failures	Skipped
CV32E40P `97086e95`	`RV32IMC_Zicsr_Zifencei_Zicntr_Zihpm`	100.0%	120	1	None	1 harness	6
CVA6 `81245a47`	`RV64IMAFDCB_Zicsr_Zifencei_Zba_Zbb_Zbc_Zbs_Zcb_Zicond_Zicntr_Zihpm`	98.6%	438	8	6 tests on known issues	2 harness	385
DarkRISCV `974034aa`	`RV32I_Zicsr`	85.1%	40	7	2 new (going to the maintainer first)	none	560
Hazard3 `8af99293`	`RV32IMAC_Zicsr_Zifencei_Zba_Zbb_Zbc_Zbs_Zcb_Zclsd_Zcmp_Zilsd`	97.7%	172	7	Fixed on develop	3 harness, 2 unresolved	9
Ibex `af456e25`	`rv32imc_zicntr_zicsr_zifencei_zihpm`	100.0%	127	2	None	2 harness	5
NEORV32 `af905649`	`rv32imacb_zicsr_zifencei_zba_zbb_zbc_zbs_zca_zcb_zcmop_zibi_zicntr_zicond_zihpm_zimop_zmmul_smcntrpmf`	100.0%	213	2	None	2 harness	216
PicoRV32 `ef203c2b`	`RV32IMC`	100.0%	78	0	None	none	529
SERV `f200eb2e`	`RV32IMCZicsr_Zifencei`	88.6%	78	11	3 new (going to the maintainer first)Discussed upstream	1 harness, 1 unresolved	34
VeeR EL2 `0169d669`	`RV32IMC_Zicsr_Zifencei_Zba_Zbb_Zbc_Zbs`	99.3%	145	3	Reported upstream	2 harness	883
VeeR EL2 in Caliptra `7b901d59`	`rv32imc_zicsr_zifencei_zba_zbb_zbc_zbs`	98.5%	133	4	Same decoder as VeeR EL2; reported upstream	2 harness, 1 unresolved	894
VexRiscv `baf7dc82`	`RV32IM_Zicsr_Zifencei`	88.1%	52	8	Documented behaviour (FENCE.I flush recipe)6 tests on known issues	1 harness	27

Run 1, October 2026: riscv-arch-test 4.1.0 (ACT4 tests through a RISCOF adapter), RISCOF 1.25.3, Sail 0.15, Verilator with an Icarus cross-check, each core at the commit shown and in its documented configuration. A harness failure is a problem in our test setup, not in the core, so *Rate leaves those out. Skipped is mostly tests for extensions a core does not claim, plus a few our harness cannot run yet. This is not an official certification. A new deviation is described here only after its maintainer has the report. Updated 10 October 2026, 08:35 UTC.